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Byte-Controlled Transfers
Byte-Controlled Transfers
In most systems, the backend ignores the byte requests from the PCI Master and simply reads all four or eight bytes
from the backend. If required, the core can make the PCI byte enables available to the backend. This significantly
reduces the read bandwidth, as shown in Figure 6-16 , where a data transfer takes place every five clock cycles. If
RD_STB_IN is asserted in the same clock cycle where BYTE_VALN is active, this can be reduced to four cycles.
The PCI Master sets the CBEN signals initially for each byte-controlled read transfer. These take one clock cycle to
propagate to the core backend on the BYTE_ENN output (active low). The core indicates the validity of these signals
by asserting the BYTE_VALN output (active low). At this point, the backend logic can perform its byte-controlled read
operation and assert RD_STB_IN. Two cycles later, the data appears on the PCI bus and the core asserts TRDYN.
Only now can the PCI Master start the next read cycle, updating the PCI CBEN lines for the next transfer, and the
whole process repeats.
cycle
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
clk
framen
cben[3:0]
6
E
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
rd_cyc
0
byte_enn[3:0]
6
E
0
byte_valn
rd_stb_out
rd_stb_in
mem_add[11:0]
mem_data_in[31:0]
000
0
004
1
008
2
00C
3
rd_sync
Figure 6-16 · Backend Byte Read Cycle (RD_SYNC = 0)
v4.0
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